Session Speaker – Semiconductor Hardware and Materials
Van der Waals Material Memory and Computing Devices
Dr. Han Wang
Associate Professor of Electrical and Computer Engineering, University of Southern California
Research Principal Investigator/Head of Low Dimensional Materials Research, Taiwan Semiconductor Manufacturing Company (TSMC) Corporate Research
Biography:
Han Wang is an Associate Professor of Electrical and Computer Engineering and holder of the Robert G. and Mary G. Lane Early Career Chair at University of Southern California (USC). Currently, he also leads the low dimensional materials research at Taiwan Semiconductor Manufacturing Company (TSMC) Corporate Research. He received the B.A. degree in electrical and information science from Cambridge University in 2007 and his PhD degree from Massachusetts Institute of Technology (MIT) in 2013. From 2013 to 2014, he was with the Nanoscale Science and Technology group at IBM T. J. Watson Research Center. His research interests include the fundamental study and device innovation in electronics and photonics technology based on emerging nanomaterials for sensing, communication and computing applications. His work has been recognized with numerous awards including the Army Research Office Young Invesitgator Award, National Science Foundation CAREER award, IEEE Nanotechnology Council Early Career Award, the Roger A. Haken Best Paper Award in IEEE International Electron Device Meeting (IEDM), USC Viterbi Junior Faculty Research Award, and the MIT Jin-Au Kong Best Doctoral Thesis Award. He is the IEEE Nanotechnology Council Distinguished Lectuer for 2020-2021, and he is also recipient of the Orange County Engineering Council (OCEC) Outstanding Educator Award for his contributions to the science and engineering education in the Los Angeles area. Dr. Wang has authored or co-authored more than 100 publications in distinguished journals and conferences.
Abstract:
In this talk, I will discuss our recent research in developing van der Waals material based memory and computing devices. Our recent work in developing high performance ferroelectric tunneling junction memory based on the layered ferroelectric CuInP2S6 (CIPS) will be discussed. A record giant TER above 107 is obtained due to the large Fermi level shift in monolayer graphene in synergy with the flipping of the ferroelectric polarization in CIPS. The large Fermi level shift (barrier height modulation (BHM), ~1 eV) is attributed to the low density of states and quantum capacitance near the Dirac point of semi-metallic graphene. This new approach for achieving ultrahigh TER in FTJ memory based on atomically-thin semimetal graphene contact is also promising for high density integration with silicon electronics. In the second part of the talk, I will discuss about our demonstration of an ultralow power resistive memory device based on oxidized boron nitride. This memristive device features sub-nm filament switching layer and can operate at record low sub-femtojoule per switching cycle, which can be attractive for low power memory and in-memory computing applications. Finally, a charge-density-wave stochastic neuronal devices based on 1T-TaS2 with reconfigurable statistical features in its output sampling will also be discussed. The device enabled the first neural network circuit implementation of Boltzmann machine for solving combinatorial optimization problem.